Fin-based field effect transistors (FINFETs) are vertical transistor devices in which a semiconductor fin is located on a substrate and is used to define the source, drain, and channel regions of the device. A gate structure overlies the fin in the channel area, and in some configurations multiple fins may be used to provide a multi-gate transistor architecture. The multiple gates may be controlled by a single gate electrode, where the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes.
FINFET devices may provide desired short channel control to enable technology scaling down to 10 nm nodes and beyond. With ever-increasing device integration densities, various challenges may arise with respect to FINFET semiconductor devices. For example, with increasing densities, the distances between adjacent devices become smaller, making the chances for inadvertent shorting between them greater.
A source/drain in-situ doped epitaxial merge process may be used to connect the fins outside of the gate for lowering the source/drain spreading resistance, and to provide a relatively flat topography for source/drain contact landings. One potential drawback of this lateral epitaxial growth in complementary devices is that in the boundary region between N-type and P-type transistors, relaxed or wider spacing may otherwise be required to keep epitaxial growth from shorting together the fins from the N-type and P-type transistors.
More particularly, due to the loading effects, the fins tend to experience more epitaxial growth, which may make it challenging to achieve desired growth in the source/drain regions without inter-fin growth that results in shorting. However, increasing the spacing between N-type and P-type devices reduces the amount of available surface area, and accordingly, restricts chip area scaling, especially in ultra-dense SRAM arrays, for example.